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MX93002
FEATURES
. Built-in two single +5V power supply PCM CODECs . Support external volume control . Support Digital Speakerphone application . Support automatic power-down function . On-chip differential line driver . On-chip ALC (automatic level control)
. Support 2.048 or 1.536 MHz master clock for 8KHz . On-chip digital volume control Frame Sync. . Support gA law and 16-bit format linear data / . Support switch paths for DAM (digital answering machine) related applications . Support two comparators for power-low and battery- low detection 7. Support external L.P.F. for D/A output path . On-chip differential 8 power amplifier . On-chip programmable receive/transmit gain control . Easy interface to general purpose DSP . Easy Read/Write of control registers by MCU . Easy interface to FAX or Cordless Phone . 44-pin PQFP/PLCC package
PIN CONFIGURATION
33332222222 32109876543 S D E N SDATA B SCLK DX1 DR1 DX2 DR2 FS MCLK VDD DGND PGND S V D D 2 S P K N S G N D S P K P SVALLP VRUPPG D XFFA D 2 CCC 1 212 44444 65432143210 S D E N SDATA B SCLK DX1 DR1 DX2 DR2 FS MCLK VDD DGND PGND S V D D 2 S P K N S VALLP PSRUPPG KV XFFA PD 2 CCC D 2 1 2 FILT ALCC2 1 ALCC1 ALCRC PGAC1 AUX1 LIN MIC VREF AG LL VBG PVBVOOAA OPABUUVG WO T A T T D N B WB T P N D D S G N D
34 35 36 37 38 39 40 41 42 43 44
P V CD PD
V C O M P
PVB OPA WO T B WB
V B A T
L O U T P
L O U T N
A V D D
FILT ALCC2 ALCC1 ALCRC PGAC1 AUX1 LIN MIC VREF AG VBG A G N D
22 21 20 19 18 17 16 15 14 13 12
7 8 9 10 11 12 13 14 15 16 17
P V CD PD
V C O M P
39 38 37 36 35 34 33 32 31 30 29
12345678911 01
11222222222 89012345678
44 PINS PQFP
44 PINS PLCC
1
Ver 2.50 September 17, 1998
MX93002
PRODUCT OVERVIEW
The MX93002 PCM CODEC integrates key functions of the analog-front-end of DAM (with Digital Speakerphone) related products into an integrated circuit. The MX93002 PCM CODEC is especially powerful when applied to some DAM models which are intended to meet different countries' specifications in the same system hardware. User can achieve this goal by simply setting control firmware. This benefit will help DAM system makers to save developing time and R&D resources. The MX93002 has two A/D, D/A converters so as to meet the requirement of the digital speakerphone application. The on-chip digital filters, which are carried out with 16-bit and 2's complement format, are used to get required frequency response of a PCM CODEC. The CODEC can support 8-bit u/A law and linear data format. For the latter, it is 16-bit format with 14-bit resolution. Before the A/D digitizing the voice-band analog signal into digital format, the analog signal can be processed by a built-in Automatic Level Control (ALC) and PRE-Programmable Gain Amplifier (PRE-PGA). The ALC circuit controls the signal level about 1.2Vpp and AD1-PGA can provide 0 ~ 18dB gain to get more larger signal. The PRE-PGA circuit is used to control the gain of different sources like MIC, AUX1 or LIN input. After the digital data is converted into analog signal by D/A converter, a fully differential line driver and speaker driver are supported to drive the telephone line and 8 speaker directly without needing any external amplifiers. Besides, the analog signal can be monitored by passing the on-chip volume control or external volume control. The MX93002 supports many switches as well. User can program the control registers of the PCM CODEC to accomplish all specific operations of DAM (with digital speakerphone function) related products. In order to let MCU (Micro controller) easily Read/Write the control registers of the MX93002, the sampling clock of the serial control data is clocked by external SCLK clock and synchronized by SDENB, where SDENB signal is coming from the MCU output port by detecting one of the rising edge of external SCLK clock.
2
MX93002
BLOCK DIAGRAM ( PQFP )
AUX-I/O FAX TXA Corelessphone TXA 22 R2 14 VREF
BUF
C7 C6 23 PGAC2
AVDD C5
VDD C4
PVDD C3
10
11 AGND
42
43 DGND
2
44 DGND
AG
SWO
FILT
AVDD AGND
VDD DGND
PVDD DGND CP
SWM
AD2 PGA
SWI
2 PCM CODECS
AIN2
MCLK
1 R1 C2 C1
41
MIC
C8 15 17 C17 16
MIC AUX1 LIN AG
SWA a b c d A
PRE PGA
SWC bA a
SWD
AD1 PGA
FS
AIN1
A I N 1 A I N 2 DR1
40
ALC
SWN SWB SWJ
37
DSP Master Clock signal DSP Frame Sync. signal DSP Transmit DATA1 DSP Receive DATA1 DSP Transmit DATA2 DSP Receive DATA2
DX1
18 C9 19
PGAC1 ALCRC ALCC1 ALCC2 LOUTP LOUTN SVDD1 SVDD2 SGND SPKP SPKN
36
+
C10 R3 C11
20 21 8
A O U T 1
A O U T 2
DR2
39
DX2
38
AOUT1 SWE LIN DRV SWL AOUT2
TELEPHONE LINE INTERFACE
9 28
AVDD
SPK
C12
32 30 29 31
SWG A SPK DRV a B
SWF ATT1
D/A PGA
SCLK
35
uP Send SCLK uP Enable SDATA uP TX / RX Control DATA uP check SYSTEM Power uP check SYSTEM Battery
L.P.F.
VR1 27 25 24 C13 C14 VR LPFC2 LPFC1
ATT2
SERIAL CONTROL UNIT
SDENB
33
SDATA
34
POW
SWK
12 C15 13 C16 AG AG VBG
SWH
BAT
POWB
4
BATB
6
AUX2 26 AUX-I/O FAX RXA Corelessphone RXA
V reference for POW and BAT 2 Comparators
VCOMP 3
AC/DC ADAPTOR
VPOW 5 R4 R5
BATTERY POWER
VBAT 7 R6 R7
3
MX93002
PIN DESCRIPTION
SYMBOL PIN TYPE PIN NBR. PQFP (PLCC) CP I (D) 1 (18) the output of internal PLL charge pump circuits; see the end of page 21 about lockin time spec. PVDD VCOMP POWB VPOW P (D) I (A) O (A) I (A) 2 (19) 3 (20) 4 (21) 5 (22) digital power supply; 5V power supply for internal PLL charge pump circuits the reference voltage for POW and BAT comparators use the output of POW comparator; active low the Non-inverting input of POW comparator; the voltage is divided from system DC power for comparison with VCOMP; with 7V Surge Protect BATB VBAT O (A) I (A) 6 (23) 7 (24) the output of BAT comparator; active low the Non-inverting input of BAT comparator; the voltage is divided from battery power for compare with VCOMP; with 7V surge protect LOUTP LOUTN AVDD AGND VBG O (A) O (A) P (A) P (A) O (A) 8 (25) 9 (26) 10 (27) 11 (28) 12 (29) the Non-inverting output of LIN-DRV with PGA; PGA from 0 to 22.5dB; 1.5dB/step the Inverting output of LIN-DRV with PGA; PGA from 0 to 22.5dB; 1.5dB/step analog power supply; 5V power supply for all internal analog circuits analog power ground band-gap reference; nominal 1.25VW and should not be used to sink or source current AG O (A) 13 (30) internal analog signal ground; nominal 2.25VW and should not be used to sink or source current VREF MIC LIN AUX1 PGAC1 ALCRC ALCC1 ALCC2 FILT O (A) I (A) I (A) I/O (A) O (A) O (A) O (A) O (A) I/O (A) 14 (31) 15 (32) 16 (33) 17 (34) 18 (35) 19 (36) 20 (37) 21 (38) 22 (39) 23 (40) voltage reference; nominal 2.25VW and can sink 450uA microphone input with PRE-PGA; PGA from -15 to 21dB;see NOTE 1 telephone line signal input with PRE-PGA; PGA from -15 to 21dB; see NOTE 1 auxiliary signal input with PRE-PGA; PGA from -15 to 21dB; see NOTE 1 programmable gain amplifier (PRE-PGA) compensative capacitor automatic level control (ALC) time constant; see FIG. 5 automatic level control (ALC) DC blocking capacitor output automatic level control (ALC) DC blocking capacitor input 1. anti-aliasing filter; 2. as an I/O port for AIN (A/D input) Programmable Gain Amplifier Offset Capacitor DESCRIPTION
PGAC2 O ( A )
4
MX93002
SYMBOL PIN TYPE PIN NBR. PQFP (PLCC) LPFC1 O (A) 24 (41) the option of the external passive L.P.F. (Low Pass Filter); if the pin is NC then will by-pass L.P.F, where L.P.F. 3dB point : fc = 1/2 k 3K (10%) CLPFC1) LPFC2 O (A) 25 (42) the option of the external passive L.P.F. (Low Pass Filter); if the pin is NC then will by-pass L.P.F, where L.P.F. 3dB point : fc = 1/2 k 3K (10%) CLPFC2) AUX2 VR SVDD1 SPKP I/O (A) O (A) P (A) O (A) 26 (43) 27 (44) 28 (1) 29 (2) as an I/O port for SWK and SWH external speaker volume control; use a 10K variable resistor analog power supply; 5V power for SPK-DRV the Non-inverting output of SPK-DRV with DA-PGA, ATT1 and ATT2; PGA from 0 to 9dB; Attenuator 1 & 2 from 0 to -45dB; see NOTE. 3 SGND SPKN P (A) O (A) 30 (3) 31 (4) analog power ground for SPK-DRV the Inverting output of SPK-DRV with DA-PGA, ATT1 and ATT2; PGA from 0 to 9dB; Attenuator 1 & 2 from 0 to -45dB; see NOTE 3 SVDD2 SDENB P (A) I (D) 32 (5) 33 (6) analog power ground for SPK-DRV the enable signal for serial control data; active low; for starting to Receive/Transmit serial control data (A2~A0,D7~D0) SDATA I/O (D) 34 (7) Bi-directional serial control data port; it is an interface for Microprocessor to Transmit/Receive serial control data SCLK I (D) 35 (8) serial control data clock; the clock source of serial control data; from microprocessor DX1 DR1 DX2 DR2 FS MCLK O (D) I (D) O (D) I (D) I (D) I (D) 36 (9) 37 (10) 38 (11) 39 (12) 40 (13) 41 (14) transmit serial data receive serial data transmit serial data receive serial data frame sync. input; 8KHz frame sync. Clock for the Transmit/Receive serial data master clock input, if MCLK is continuously high or low then the MX93002 will get into power down mode automatically VDD DGND PGND P (D) P (D) P (D) 42 (15) 43 (16) 44 (17) digital power supply; 5V power supply for all internal digital logic digital power ground digital power ground; for internal PLL charge pump circuits DESCRIPTION
@ PIN TYPE : " I" : Input Port; " O" : Output Port; " I/O" : Bi-direction Port; " P" : Power " (D)" : Digital Pin; " (A)" : Analog Pin
5
MX93002
BASIC COMPONENTS REQUIRED
REFERANCE *R1 R2 R3 R4, R5 R6, R7 *C1 *C2 C8, C17 C11 100pF 6pF 0.1uF 0.22uF PART 68K 2K 560K DESCRIPTION the resistor for internal PLL charge pump circuits current limit resistor; to limit MIC bias current, please follow MIC specification ALC release time constant; see FIG. 10 to scale down DC power supply (VPOW) for reference to VCOMP to check power low to scale down battery power (VBAT) for reference to VCOMP to check battery low the capacitor for internal PLL charge pump circuits the capacitor for internal PLL charge pump circuits DC blocking capacitor (0.1~10uF) DC blocking capacitor (0.1~10uF); H.P.F. 3dB point : fc U 1/2 k 4.4K C6 (0.22uF) = 164Hz C6 C9 C3, C4, C5, C12, C16 C15 C10 *C7 C13, C14 *VR1 10K 0.1uF 10uF De-couple capacitor (0.01~10uF); see FUNCTIONAL DESCRIPTION ALC attack time constant; see FIG. 9 passive L.P.F.; 3dB point : fc U 1/2 k 3K C13 (where C13 = C14) to attenuate the input signal from SWH or SWF, if use digital volume control, then do not need a resistor between VR and SPKP @ where : " * " mark shows the requirement of the component can not be changed. 10uF 0.1uF 0.1uF DC offset canceling compensative capacitor (4.7~10uF, the larger the better) DC offset canceling compensative capacitor (0.1~1uF, the larger the better) De-couple capacitor (0.1~10uF)
5000pF anti-aliasing capacitor
6
MX93002
FUNCTIONAL DESCRIPTION
. Clock Rate (REG4 bit(2))
. The clock rate (MCLK) must be set before user uses the function of the MX93002; . Programmable clock rate : 1. 2.048MHz (Frame Sync. 8KHz); 2. 1.536MHz (Frame Sync. 8KHz);
. Data Format (REG4 bit(1,0))
. The data format must be set before user uses the function of the MX93002; . Programmable Data Format 1. 16-bit linear data format. It can have 14-bit resolution and higher linearity than u/a-law format has; 2. 8-bit u-law data format; 3. 8-bit a-law data format;
. PCM CODEC
. The block includes A/D & D/A converters and all digital filters; 1. A/D & D/A Converters A/D Channel : A. Input Range : 0 ~ 3Vpp (3Vpp as A/D 0dB full swing (0dBFS)); B. Digital Filters : For the purpose of out-of-band noise filtering, IIR digital filters are implemented on the same chip ( >26dB / 60Hz; <1dB / 300Hz ~ 3.4KHz; >14dB / 3.6KHz ~ 4.6KHz; >32dB / >4.6KHz ); D/A Channel : A. Output swing : 0 ~ 3Vpp (3Vpp as D/A 0dB full swing (0dBFS)); B. Digital Filters : a. G.711 specification; b. The digital input applied to D/A converter can not be a DC signal other than idle (bits all zero), as limit cycles in the embodiment method at a level of -70dBm will present at the analog output.
. Power Down Mode
. The MX93002 will recover from power-down mode when MCLK keeps a consistent clock (1.536 or 2.048MHz); . Support system power (Adapter and Battery) detection. The function will work well even under 3V power supply; . Support automatic power-down control when MCLK keeps high or low; . Support 4 power-down modes for special applications: MODE FUNCTION VBG reference POW & BAT all analog blocks A/D and D/A
REG 6 (7,6) REG 6 (7,6) REG 6 (7,6) REG 6 (7,6)
(SLEEPA,SLEEP) = ( 0,0 ) (SLEEPA,SLEEP) = ( 0,1 ) (SLEEPA,SLEEP) = ( 1,0 ) (SLEEPA,SLEEP) = ( 1,1 )
on on off off
off off off off Table 1
off on off off
on on on off
7
MX93002
. 3-Channel Input (MIC,AUX1,LIN) with PRE-PGA (Pre-Programmable Gain Control)
. Input Range : 0 ~ AVDD-2Vpp; . PRE-PGA gain step from 21dB to -15dB (21, 18, 15, 12, 9, 7.5, 6, 4.5, 3, 0, -3, -6, -9, -12, -15dB); . Driving Capacity : more than 400uA at FILT and AUX2 output; . Input Impedance : more than 25K; . THD : less than 70dB at FILT output; . There is just one path which can be selected at the same time; . The gain setting of the path will be mapped to the PRE-PGA when user changes the path of Input.
. ALC (Automatic Level Control)
VOUT ( mVpp )
. Input Range : 0 ~ 1.2Vpp (Loop Gain : 40dB); . Output Characteristic : see FIG. 5 ~ FIG. 7; . Loop Gain : 42dB max (with external RC time constant); . Driving Capacity : more than 400uA at FILT and AUX2 output; . THD : less than 40dB at FILT output (Loop Gain : 40dB).
3000mVpp
1000mVpp
10mVpp
1200mVpp
VIN ( mVpp )
. AD1 PGA
. Input Range : 0 ~ AVDD-2Vpp; . AD1-PGA can support gain step from 0dB to 18dB (0, 4, 8, 18dB);
. AD2 PGA
. Input Range : 0 ~ AVDD-2Vpp; . AD2-PGA can support gain step from -6dB to 39dB (-6, -3, 0, 3, 6, 9, 12, 15, 18, 21, 24, 27, 30, 33, 36, 39dB);
. FILT as I/O Port
. Input Range : 0 ~ AVDD-2Vpp; . Input Impedance : more than 1K; . Output Impedance : less than 1K; . Load Capacitance : 5000pF;
. AUX1 & AUX2 as I/O Port
. Input Range : 0 ~ AVDD-2Vpp; . Input Impedance : more than 15K; . Output Impedance : less than 15K;
. External passive L.P.F. (Low Pass Filter)
. External capacitors (LPFC1 and LPFC2) can be changed to attenuate high frequency noise at SPKP and SPKN output; . When external capacitors (LPFC1 and LPFC2) are NC (no connection), then passive L.P.F. will be by-passed; . Output of the Line Driver (LOUTP and LOUTN) can be chosen to pass or by-pass the L.P.F.; . LPFC1/LPFC2 can be a D/A output pin and output impedance is around 3K/6K;
8
MX93002
. Line Driver (LIN-DRV)
. Not only support the programmable gain from 0 to 22.5dB, but also fully differentially drive 6Vpp over 600; . If switches SWE, SWJ, SWK and SWL are opened, then the line driver will be muted to -70dB and power-down automatically; 1. output swing : Single Ended (only use LOUTP or LOUTN) : 0 ~ 3Vpp (over 600 load, at LIN-DRV = 0dB); Fully differential (use LOUTP + LOUTN) : 0 ~ 6Vpp (over 600 load, at LIN-DRV = 0dB); 2. LIN-DRV gain step from 0dB to 22.5dB (1.5dB/step); 3. THD : less than 70dB at 6Vpp output over 600 load;
. D/A PGA
. Input Range : 0 ~ AVDD-2Vpp; . DA-PGA can support gain step from 0dB to 6dB (2dB/step);
. Attenuator (ATT1 & ATT2)
. Speaker output signal can be attenuated either by internal register or external resistor; . If switches SWF and SWH are opened, then attenuator will be muted to -70dB automatically; 1. ATT1 (internal register) : 16 steps programmable, from -45dB to 0dB (-45, -39, -33, -27, -24, -21, -18, -15, -12, -9, -7.5, -6, -4.5, -3, -1.5, 0dB); 2. ATT2 (external variable resistor) : from -45 ~ 0dB (determined by external 10K potentiometer); 3. THD : less than 70dB; 4. input range for AUX2 : 0 ~ AVDD-2Vpp; 5. input impedance for AUX2 : more than 15K;
. Speaker Driver (SPK-DRV)
. If switches SWF and SWH are opened, then SPK-DRV will be power-down automatically; 1. Maximum output swing : 6Vpp with 8 load at fully differential output (SPKP + SPKN); 2. THD : less than 60dB (at 6Vpp/8 load);
. Voltage Reference (VREF & VAG)
. Two 2.25VW voltage references are on-chip generated, where VREF is for external circuit use and VAG is for internal circuit use; . VREF can be used to bias the microphone, the level shift circuit or other applications; 1. VREF driving capacity : more than 400uA; 2. User can use the VREF to provide DC bias to external components;
. Bandgap Reference (VBG)
. A bandgap circuit generates a voltage source (VBG) which is around 1.2VW. It is with low temperature coefficient and good power supply rejection; . If user changes VBG bypass capacitor (C15) then the MX93002 warm-up time will be changed; see The Timing Diagram of CODEC Function;
9
MX93002
. Serial Control Interface
. Use SCLK for synchronization with SDATA to read/write the internal control registers; . All registers will keep original setting when the MX93002 returns from power-down or sleep mode; 1. When SDENB (serial data enable) signal active low, the MX93002 starts to receive serial control data (SDATA); 2. Set SDENB from low to high when transmitting SDATA is complete; 3. SDATA format : 3 addresses from A2 to A0, 8 data from D7 to D0 (A2 is MSB and D0 is LSB);
. Two Comparators for System Applications (RING and CPC)
. To detect Ring and CPC (Calling Party Control) or other applications; 1. input range : 0 ~ AVDD-2Vpp (with 7V surge protection); 2. input impedance : more than 10^12 ; 3. input offset voltage : less than 10mV; 4. output impedance : less than 10K; 5. slew rate : 3V/us max.;
. Switches
. There are three registers (REG0, REG3 and REG6) which are used to control all of the switches so that user can direct many different signal paths, for examples: 1. Record signal from MIC and play signal to SPKP/N or play signal to LOUTP/N: A. Record signal from MIC or Record signal from LIN: a. System initialization [set MIC gain (REG2 bit(3~0)), set LIN gain (REG1 bit(7~4), set ALC gain 0/6dB (REG5 bit(1)) and set A/D-PGA gain (REG6 bit(1,0))] b. Record signal from MIC : set REG0 = 0X0048 MIC SWA PRE-PGA SWC (ALC on) SWD AD1-PGA PCM CODEC AIN1 c. Record signal from LIN : set REG0 = 0X00C8 LIN SWA PRE-PGA SWC (ALC on) SWD AD1-PGA PCM CODEC AIN1 B. Play signal to SPKP/N or play signal to LOUTP/N: a. System initialization [fix the value of L.P.F. , set (REG6 bit(5)), set D/A-PGA gain (REG6 bit(3,2), set ATT1 gain (REG3 bit(3~0)) and LIN-DRV gain (REG1 bit(3~0))] b. Play signal to SPKP/N (use digital volume control) : set REG 0 = 0X0003 PCM CODEC AOUT1 L.P.F. SWF DA-PGA SWG (ATT1) SPK-DRV SPKP/N c. Play signal to LOUTP/N : set REG 0 = 0X0004 i. PCM CODEC AOUT1 L.P.F. SWL LIN-DRV LOUTP/N ii. PCM CODEC AOUT2 SWE LIN-DRV LOUTP/N d. Play signal to SPKP/N (use digital volume control) and LOUTP/N : set REG 0 = 0X0007 i. PCM CODEC AOUT1 L.P.F. SWF DA-PGA SWG (ATT1) SPK-DRV SPKP/N PCM CODEC AOUT2 SWE LIN-DRV LOUTP/N ii. PCM CODEC AOUT1 L.P.F. SWF DA-PGA SWG (ATT1) SPK-DRV SPKP/N SWL LIN-DRV LOUTP/N
10
MX93002
2. Room Monitoring: A. System initialization [set MIC gain (REG2 bit(3~0)), set ALC gain 0/+6dB (REG5 bit(1)), set LIN-DRV gain (REG1 bit(3~0)), set REG3 bit(6,5) and set REG6 bit(1,0)] B. Switches path: a. Remote Monitoring: MIC SWA PRE-PGA SWC (ALC on) SWJ LIN-DRV LOUTP/N b. Local Detecting DTMF: LIN SWI AD1-PGA PCM CODEC AIN1 3. Digital Speakerphone: A. System Initialization [set MIC gain (REG2 bit(3~0)), set AD1-PGA gain (REG6 bit(1,0)), fix the value of L.P.F., set DA-PGA gain (REG6 bit(3,2)), set ATT1 gain (REG3 bit(3~0)), set LIN gain (REG1 bit(7~4)), set SWM REG4 bit(4), set LIN-DRV gain (REG1 bit(3~0))] B. Switches path : set REG0 = 0X00AF a. CODEC 1 : Record signal from MIC and Play signal to SPKP/N (use digital volume control) MIC SWA PRE-PGA SWC (ALC off) SWD AD1-PGA PCM CODEC AIN1 PCM CODEC AOUT1 L.P.F. SWF SWG (ATT1) SPK-DRV SPKP/N b. CODEC 2 : Record signal from LIN and Play signal to LOUTP/N LIN SWM AD2-PGA PCM CODEC AIN2 PCM CODEC AOUT2 SWE LIN-DRV LOUTP/N
. Power Consumption (with 600 line load and 8 speaker load)
Max. Power Consumption Operation Stand-by Operating Disable Disable Enable Disable Enable Disable Disable Disable Disable Disable Enable Enable Disable Disable 27 27 31 240 250 460 20 8 8 8 8 8 335 400 mA mA LIN-DRV Dis/Enable SPK-DRV Dis/Enable Analog circuits Digital circuits Unit
Power-down Power-down with SLEEP = 1
uA uA
@ Test condition : 1. at LIN-DRV (with 600 load) / SPK-DRV (with 8 load) full swing output 2. see LIN-DRV and SPK-DRV Descriptions 3. at the case of Temperature from -2 J 72 J to and Voltage from 4.4V to 5.6V
11
MX93002
CONTROL REGISTERS DEFINITION
REGISTER 0
ADDRESS BIT DATA DATA BIT POWER-ON DESCRIPTION A2 0 D7 0 SWA A1 0 D6 0 A0 0 D5 0 SWB D4 0 SWC D3 0 SWD D2 0 SWE D1 0 SWF D0 0 SWG
( SWA ) D(7,6) = (1,1) : path of SWA is "c A", PRE-PGA setting follows LIN GAIN SETTING = (1,0) : path of SWA is "b A", PRE-PGA setting follows AUX1 GAIN SETTING = (0,1) : path of SWA is "a A", PRE-PGA setting follows MIC GAIN SETTING = (0,0) : path of SWA is "d A", (GROUNDING to AG) ( SWB ) D(5) = (1) : path of SWB is "CLOSE", D(5) = (0) : path of SWB is "OPEN" ( SWC ) D(4) = (1) : path of SWC is "b A", D(4) = (0) : path of SWC is "a A" ( SWD ) D(3) = (1) : path of SWD is "CLOSE", D(3) = (0) : path of SWD is "OPEN" ( SWE ) D(2) = (1) : path of SWE is "CLOSE", D(2) = (0) : path of SWE is "OPEN"; see NOTE 4 ( SWF ) D(1) = (1) : path of SWF is "CLOSE " , D(1) = (0) : path of SWF is " OPEN " ( SWG ) D(0) = (1) : path of SWG is "a A", ATTENUATOR 1 (ATT1) = (0) : path of SWG is "a B", ATTENUATOR 2 (ATT2)
REGISTER 1
ADDRESS BIT DATA DATA BIT POWER-ON DESCRIPTION A2 0 D7 0 A1 0 D6 0 A0 1 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
LIN GAIN SETTING ( PRE-PGA )
LIN-DRV GAIN SETTING
( LIN GAIN SETTING ) D(7~4) = (F) ~ (0) : 21dB ~ -15dB; see NOTE 1 ( LIN-DRV GAIN SETTING ) D(3~0) = (F) ~ (0) : 22.5dB ~ 0dB 1.5dB/step; see NOTE 2
REGISTER 2
ADDRESS BIT DATA DATA BIT POWER-ON DESCRIPTION A2 0 D7 0 A1 1 D6 0 A0 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
AUX1 GAIN SETTING ( PRE-PGA )
MIC GAIN SETTING ( PRE-PGA )
( AUX1 GAIN SETTING ) D(7~4) = (F) ~ (0) : 21dB ~ -15dB; see NOTE 1 ( MIC GAIN SETTING ) D(3~0) = (F) ~ (0) : 21dB ~ -15dB; see NOTE 1
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MX93002
REGISTER 3
ADDRESS BIT DATA DATA BIT POWER-ON DESCRIPTION A2 0 D7 0 SWH A1 1 D6 0 SWI A0 1 D5 0 SWJ D4 0 SWK D3 1 D2 1 D1 1 D0 1
ATT1 GAIN SETTING
( SWH ) D(7) = (1) : path of SWH is "CLOSE", D(7) = (0) : path of SWH is "OPEN" ( SWI ) D(6) = (1) : path of SWI is "CLOSE", D(6) = (0) : path of SWI is "OPEN" ( SWJ ) D(5) = (1) : path of SWJ is "CLOSE", D(5) = (0) : path of SWJ is "OPEN" ( SWK ) D(4) = (1) : path of SWK is "CLOSE", D(4) = (0) : path of SWK is "OPEN" ( ATT1 GAIN SETTING ) D(3~0) = (F)~(0) : - 45dB ~ 0dB; see NOTE 3
REGISTER 4
ADDRESS BIT DATA DATA BIT POWER_ON DESCRIPTION A2 1 D7 0 A1 0 D6 1 A0 0 D5 0 D4 1 D3 1 SWM D2 0 RATE D1 0 D0 0
AD2-PGA GAIN SETTING
DATA FORMAT
( AD2-PGA GAIN SETTING ) D(7~4) = (0) ~ (F) : -6dB ~ 39dB; see NOTE 3 ( SWM ) D(3) = (1) : path of SWM is "CLOSE", D(3) = (0) : path of SWM is "OPEN" ( RATE ) D(2) = (1) : master clock (MCLK) use 1.536MHz, D(2) = (0) : master clock (MCLK) use 2.048MHz ( DATA FORMAT ) D(1,0) = (1,1),(1,0) : Linear Coder/Decoder (16-bit format) = (0,1) : a-Law Coder/Decoder (8-bit format) = (0,0) : u-LAW Coder/Decoder (8-bit format) @ Linear 16-bit format : 14-bit resolution with 2 LSB = 0 SIGN \ SCALE POSITIVE NEGATIVE MIN 0000 0000 0000 0000 1111 1111 1111 1100 MAX 0111 1111 1111 1100 1000 0000 0000 0000
REGISTER 5
ADDRESS BIT DATA DATA BIT POWER_ON DESCRIPTION A2 1 D7 0 ALC1 A1 0 D6 0 SPKHI A0 1 D5 0 ADA D4 0 AIADID D3 0 DAYT D2 0 ADYT D1 0 ALC0 D0 0 TDSPCK
D ( 5 ~ 2 and 0 ) : reserved ( SPKHI ) D(6) = (0) : SPKP/N can drive 8 load when SPK-DRV turns on D(6) = (1) : SPKP/N appears high impedance (10K) and SPK-DRV will keep a quiescent current when
13
MX93002
SPK-DRV turns on ( ALC1 , ALC0 ) D(7,1) = (0,0) : ALC open loop gain is 38dB = (0,1) : ALC open loop gain is 42dB = (1,0) : reserved = (1,1) : external ALC option ( PRE-PGA Output : ALCC1, SWC path " a" Input : ALCC2)
REGISTER 6
ADDRESS BIT DATA DATA BIT POWER_ON DESCRIPTION A2 1 D7 0 SLEEPA A1 1 D6 0 SLEEP A0 0 D5 0 SWL D4 0 SPKMUTE D3 0 D2 0 D1 0 D0 0
SPK-DRV GAIN SETTING
AD1-PGA GAIN SETTING
( SLEEPA , SLEEP ) D(7,6) = (0,0) : when the MX93002 gets into power down mode, all the blocks of the MX93002 will be disabled except the VBG reference and 2 comparators (POW, BAT) D(7,6) = (0,1) : when the MX93002 gets into power down mode, all the blocks of the MX93002 will be disabled D(7,6) = (1,0) : when the MX93002 gets into power down mode, all the blocks of the MX93002 will be disabled except 2 comparators (POW, BAT) D(7,6) = (1,1) : when the MX93002 gets into power down mode, all the analog blocks of the MX93002 will be still functional and can be programmed by control registers ( SWL ) D(5) = (1) : path of SWL is "CLOSE", D(5) = (0) : path of SWL is "OPEN" ; see NOTE 7 ( SPK-MUTE ) D(4) = 1 : force SPK-DRV mute to -70dB, D(4) = 0 : force SPK-DRV un-mute ( SPK-DRV GAIN SETTING ) D(3,2) = (0,0) ~ (1,1) : 0dB ~ 8dB; 2dB/step; see NOTE 5 ( AD1-PGA GAIN SETTING ) D(1,0) = (0,0) ~ (1,1) : 0dB ~ 18dB; see NOTE 2
REGISTER 7
ADDRESS BIT DATA DATA BIT POWER_ON DESCRIPTIN A2 1 D7 0 A1 1 D6 0 A0 1 D5 0 SWO D4 0 SWN D3 0 READ D2 0 D1 0 D0 0
REGISTER ADDRESS
( SWO ) D(5) = (1) : path of SWO is "CLOSE", D(5) = (0) : path of SWO is "OPEN" ( SWN ) D(4) = (1) : path of SWN is "CLOSE", D(5) = (0) : path of SWN is "OPEN" ; see NOTE 7 ( READ ) D(3) = 1 : read data from Register 0 ~ 7, D(3) = 0 : write data to Register 0 ~ 7 ( REGISTER ADDRESS ) D(2~0) : When READ = 1, then a. READ will be cleared automatically; b. if next uP SDENB signal active low, the content of REGISTER ADDRESS will be dumped out through CODEC SDATA interface;
14
MX93002
SPECIFICATIONS
Absolute Maximum Rating
PARAMETER AVDD to AGND VDD to DGND Voltage at any Digital Input or Output Current at any Digital Input or Output Operating Ambient Temperature Range Storage Temperature Range Lead Temperature ( Soldering, 10 seconds ) MIN -0.3 -0.3 DGND-0.3 0 -65 TYP MAX 6.0 6.0 VDD+0.3 8 70 150 UNITS V V V mA J J
Power Supply
PARAMETER Power Supply Voltage : Digital and Analog Power Supply Current : Stand-by : Digital Analog Operating : Digital Analog ( see Page 11) Power-Down : Digital Analog ( at REG4 bit 6 SLEEP = 0 ) Analog ( at REG4 bit 6 SLEEP = 1 ) 8 255 400 460 20 mA mA uA uA uA 4.5 5.0 5.5 V MIN TYP MAX UNITS
8 27
mA mA
Electrical Characteristics ( BOLD characters are guaranteed for AVDD = VDD = 5V 5%, temperature =
0 ~ 70 J Typical specified at AVDD = VDD = 5V, temperature = 25 J " *" mark : guaranteed by . . design )
Digital Interface
PARAMETER High Level Input Voltage ( VIH ) Low Level Input Voltage ( VIL ) High Level Output Voltage ( VOH ) Low Level Output Voltage ( VOL ) Input Low Current ( IIL ) MIN 2.2 0.6 2.4 -10 2 0.4 10 TYP MAX UNITS V V V V uA
15
MX93002
Input High Current ( IIH ) -10 10 uA
Analog Input Ports
PARAMETER MIC / LIN / AUX1 : Input Voltage * Input Capacitance * Input Impedance 3.0 15 20 Vpp pF K MIN TYP MAX UNITS
Analog Output Ports
PARAMETER Line Driver : Gain Range Step Size Step Variation Fully Differential (LOUTP+LOUTN) Full Swing / with 600 load Single Ended (LOUTP) Full Swing / with 600 load * External Load Capacitance * Output Impedance Speaker Driver : Fully Differential (SPKP+SPKN) Full Swing / with 8 load Single Ended (SPKP) Full Swing / with 8 load * External Load Capacitance * Output Impedance the Quiescent current (when REG5 bit(6) SPKHI = 1) 6.0 3.0 100 8 4 Vpp Vpp pF mA 0 1.5 10 6.0 3.0 200 600 22.5 dB dB % Vpp Vpp pF MIN TYP MAX UNITS
Analog I/O Ports
PARAMETER FILT : as Input Port : * Input Capacitance * Input Impedance as Output Port : * External Load Capacitance * Output Impedance AUX2 : as Input Port : * Input Capacitance * Input Impedance as Output Port : * External Load Capacitance 15 15 15 pF K pF 5000 1 5000 1 pF K pF K MIN TYP MAX UNITS
16
MX93002
* Output Impedance 15 K
Gain Variation
PARAMETER PRE-PGA : Gain Range Step Size Step Variation AD1-PGA : Gain Range Step Size Step Variation AD2-PGA : Gain Range Step Size Step Variation DA-PGA : Gain Range Step Size Step Variation 0 2 10 6 dB dB % -6 3 10 39 dB dB % 0 4, 10 10 18 dB dB % -15 1.5, 3 10 22.5 dB dB % MIN TYP MAX UNITS
Attenuator
PARAMETER Attenuator 1 ( Digital Volume ) : Gain Range Step Size Step Variation * Mute Attenuation Attenuator 2 ( External Volume ) : Gain Range the Requirement of External Resistor ( from SPKP to VR ) * Mute Attenuation -45 10 -57 0 dB K dB -57 -45 6, 3, 1.5 10 0 dB dB % dB MIN TYP MAX UNITS
Bandgap ( VBG pin )
PARAMETER Output Voltage * Output Current MIN 1.16 TYP 1.2 Hi-z MAX 1.24 UNITS V
Voltage Reference ( VREF pin )
PARAMETER MIN TYP MAX UNITS
17
MX93002
Output Voltage * Output Current 2.0 2.25 450 2.5 V uA
Two Operational Amplifier / Comparators ( RING, CPC )
PARAMETER * Input Offset Voltage * Input Voltage * Input Impedance * Output Impedance * Open Loop Gain * Unit Band Gain Width * Slew Rate * Input Comm. Mode Range MIN TYP MAX 10 7 10^12 10 78 2 3 3.5 UNITS mV V K dB MHz V / us V
Two Comparators ( POW, BAT )
PARAMETER Input Voltage (VCOMP, VPOW, VBAT) * Hysteresis * Output Impedance of POWB and BATB pins MIN TYP 15 10 MAX AVDD UNITS V mV K
18
MX93002
TIMING DESCRIPTION
TIMING 1/Tmck Trmck Tfmck Tfs Tfsh Tdxs Tdrh1 Tdrh2 DESCRIPTION frequency of master clock (from Vmckh1 to next Vmckh1) at RATE = 0 rise time of master clock fall time of master clock from Vmckh1 to Vfsh1 holding time for frame sync. From Vfsh1 to Vfsh2 setting time for CODEC transmit data from Vmckh1(n) to DX(n) data ready holding time for CODEC received data from DR(n) data ready to Vmckh2(n) holding time for CODEC received data from Vmckl(n) to DR(n) ending MIN TYP MAX UNIT
1.638 2.048 2.560 50 50 0 MCLK 110 0 150
MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Tupen1 from Vsclkh1 to Venl Tupen2 from Vsclkh1 to Venh Tups1 setting time for uP transmitting SDATA from Vupenl to uP SDATA(n) ready ( @ where Tupen1+Tups1 must < SCLK ) Tups2 setting time for uP transmitting SDATA from Vsclkh1(n+1) to uP SDATA(n+1) ready Tuph holding time for uP transmitting SDATA from Vsclkh1(n+1) to uP SDATA(n) ending Tcdrd from Vsclkh1(n+1) to CODEC reading SDATA(n) Tupo2i from Vupenl to uP changing its SDATA interface to input port Tcdi2o from Vsclkh1 to CODEC changing its SDATA interface to output port Tcds1 setting time for CODEC transmitting SDATA from Vcdi2o to SDATA(n) ready Tcds2 setting time for CODEC transmitting SDATA from Vsclkh1(n+2) to SDATA(n+1) ready Tcdh holding time for CODEC transmitting SDATA from SDATA(n) ready to Vsclkh1(n+2) Tcdo2i from Venh to CODEC changing its SDATA interface to input port Tuprd from Vsclkh1(n+1) to uP reading SDATA(n) Tupi2o from Vsclkh1 to uP changing its SDATA interface to output port Vmckh1 logic high when CODEC MCLK rising Vmckh2 logic high when CODEC MCLK falling Vmckl logic low when CODEC MCLK falling Vfsh1 logic high when CODEC FS rising Vsclkh1 logic high when SCLK rising Vcdi2o CODEC changes its SDATA interface to output port Venh Venl logic high when uP SDENB rising logic low when uP SDENB falling
40 40 40
SCLK SCLK SLCK
40
SCLK
40
Tups2
20
40
FS 20 20
20
SCLK
20 40 40 SCLK FS
19
MX93002
TIMING DIAGRAM
Master Clock, Frame Sync. & Data Timing Diagram
MCLK FS
MSB LSB 2 3 4 5 6 7 8 9 11 u-law : H , a-law : L LSB 2 3 4 5 6 7 8 10 12 13 14 15 16 L 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6
u/a-law DR / DX Linear DR / DX Vmckh1
1 MSB 1
MCLK Tfs FS DX
Vfsh1
Vmckh2 Vmckl
Vmckh1 (n)
(n+1)
1
Tfsh
Vfsh2
2
Tdxs
Tdxs
1(n)
Tdrh1
2 (n+1)
Tdrh2
DR
1 (n)
Vsclkh1 n n+1 n+2
2 (n+1)
1 0 1 1 1 2 1 3 Tupen2
Venh
Control Registers R/W Timing Diagram
CODEC READ SDATA SCLK
1
2
Tups1 Tuph
3
4
5
6
Tuph Tups2
7
8
9
SDENB
Tupen1 Venl
uP SDATA interface CODEC SDATA interface CODEC WRITE SDATA
A2
n
A1
n+1 Tcdrd
A0
D7
D6
D5
D4
D3
D2
D1
D0
CODEC read SDATA
Vsclkh1 n
n+1
n+2
SCLK
1
2
Tupen1 Vcdi2o Tcdi2o Tcds1
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
Tupen2
SDENB CODEC SDATA interface
Tcds2 Tcdh
Tcdo2i
A2
Tupo2i n
n+1 Tuprd
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Tupi2o
uP SDATA interface
uP read SDATA
20
MX93002
The Timing Diagram of CODEC Function
(SLEEPA,SLEEP) = (0,0) or (1,1)
tA
VDD AVDD VBG MCLK VAG CP Register R/W A/D and D/A Analog Paths Analog Paths POW, BAT 2 OPs
(SLEEPA,SLEEP) = (0,0) (SLEEPA,SLEEP) = (1,1)
tB
tC tD tE
tF
tG tH t I
tJ tK tL
tM
~ 1.2V
power-down MCLK keeps Hi or Lo
@ Analog Paths : Analog I/O, Switches, PGA and Attenuator @ : Stable
(SLEEPA,SLEEP) = (0,1) or (1,0)
ta
VDD AVDD VBG MCLK VAG CP Register R/W A/D and D/A Analog Paths POW, BAT 2 OPs POW, BAT 2 OPs
(SLEEPA,SLEEP) = (0,1) (SLEEPA,SLEEP) = (1,0)
tb
tc td te
tf
tg th
ti tj
tk tl tm
tn
~ 3.4V ~ 1.2V power-down MCLK keeps Hi or Lo
@ Analog Paths : Analog I/O, Switches, PGA and Attenuator @ : Stable
21
MX93002
The Timing Description of CODEC Function
TIMING tA, ta tC VDD / AVDD U 3.0VDC MCLK started DESCRIPTION MIN TYP MAX UNIT
tC tG MCLK keeps tc tg tG, tg tJ, tl Power-down started ( MCLK keeps High or Low ) Power-down ended ( MCLK started )
tF t I MCLK keeps High or Low tA tB the charge time of VBG ( where VBG bypass cap. = 0.1uF ) ta tb tC tD the charge time of internal clock detector circuit tJ tK tc td tk tl tD tE the lock-in time of PLL ( C1=100pF, C2=6pF, R1=68K ) tK tL td te tl tm tD tF the charge time of VAG ( where VAG bypass cap. = 0.1uF ) tK tM td tf tG tH the discharge time of internal clock detector circuit tg th tH tI the discharge time of VAG ( where VAG bypass cap. = 0.1uF ) th tj th ti the delay time of VBG disable ( where VBG bypass cap. = 0.1uF ) tl tn the re-charge time of VBG ( where VBG bypass cap. = 0.1uF ) the re-charge time of VAG ( where VAG bypass cap. = 0.1uF ) @ when change VBG bypass capacitor (C15) : i. from 0.1uF to 1uF : (tA tB)' U (tA tB) 10 ii. from 0.1uF to 0.01uF : (tA tB)' U 1/10 (tA tB) 0.3 6 400 0.5 10 500 50 110 140 190 290 20 ms us
160
us
1.5
2
2.5
ms
50 0.7 15 700
us ms ms ms
22
MX93002
A/D Path Characteristics ( 0dBFS : reference to Fin = 1.02KHz and A/D Input is Full Swing )
PARAMETER Dynamic Range ( at -51dBFS ) THD+N ( at Vin = -6dBFS ) Interchannel Isolation of LIN/MIC/AUX1 ( at Vin = 0dBFS ) Gain Variation ( at Vin = -6dBFS ) Max. Overload Level Frequency Response ( Measure Respone from 60Hz to 4000Hz, see FIG. 3 ) : 60Hz 150Hz 200Hz 300 ~ 3200Hz 3400Hz 3600Hz 3800Hz 4000Hz 4500Hz and Up MIN 77 -56 76 -0.3 3.0 3.25 0.3 3.50 TYP MAX UNITS dB dB dBFS dBFS Vpp
-25 -7 -3 -0.8 -1.60 -4.5 -10.3 -45 -69.5
-28 -8 -4 +0.8 -1.85 -10.7
dB dB dB dB dB dB dB dB dB
D/A Path Characteristics ( 0dBFS : reference to Fout = 1.02KHz and D/A Output is Full Swing )
PARAMETER Dynamic Range ( at -51dBFS ) THD+N ( at Vin = -6dBFS ) Gain Variation ( at Vin = -6dBFS ) Out of Band Energy ( with 1.02KHz Image ) : 3.8KHz ~ 20KHz Output Level ( at AUX2 ) Frequency Response ( Measure Respone from 60Hz to 3800Hz, see FIG. 4 ) : 60Hz ~ 300Hz 300Hz ~ 2800Hz 3000Hz 3200Hz 3400Hz 3600Hz 3800Hz - 0.6 -1.1 -2.1 -3.7 -6.3 -10 -0.1 + 0.1 dB dB dB dB dB dB dB MIN 77 -47 0.1 -46 3.0 TYP MAX UNITS dB dB dBFS dBFS Vpp
23
MX93002
Noise ( Test Condition : 1. A/D 1 or 2 Input Signal is 1.02KHz/0dB (Full Swing)
2. D/A 1 or 2 Output Signal is 1.02KHz/0dB (Full Swing ) ) PARAMETER Idle-Channel Noise ( Input Grounded and Measurement Bandwidth from 0 to 4000Hz ) : A/D Path D/A Path VDD Power Supply Rejection (A/D & D/A Input Grounded and VDD = 5.0VDC+100mVrms) : A/D Channel : (Test Condition 1) Fin = 0 ~ 4KHz Fin = 4 ~ 25KHz Fin = 25 ~ 50KHz D/A Channel : (Test Condition 2) Fin = 0 ~ 4KHz Fin = 4 ~ 25KHz Fin = 25 ~ 50KHz AVDD Power Supply Rejection (A/D & D/A Input Grounded and AVDD = 5.0VDC+100mVrms) : A/D Channel : (Test Condition 1) Fin = 0 ~ 4KHz Fin = 4 ~ 25KHz Fin = 25 ~ 50KHz D/A Channel : (Test Condition 2) Fin = 0 ~ 4KHz Fin = 4 ~ 25KHz Fin = 25 ~ 50KHz Crosstalk : A/D 1 to A/D 2 (Test Condition 1) A/D 1 to D/A 1 (Test Condition 1) A/D 1 to D/A 2 (Test Condition 1) A/D 2 to A/D 1 (Test Condition 1) A/D 2 to D/A 1 (Test Condition 1) A/D 2 to D/A 2 (Test Condition 1) D/A 1 to A/D 1 (Test Condition 2) D/A 1 to A/D 2 (Test Condition 2) D/A 1 to D/A 2 (Test Condition 2) D/A 2 to A/D 1 (Test Condition 2) D/A 2 to A/D 2 (Test Condition 2) D/A 2 to D/A 1 (Test Condition 2) -77 -92 -79 -86 -86 -86 -100 -94 -86 -99 -94 -86 dB dB dB dB dB dB dB dB dB dB dB dB -71 -76 dB dB MIN TYP MAX UNITS
-54 -80 -82 -65 -80 -95
dB dB dB dB dB dB
-72 -85 -87 -41 -53 -60
dB dB dB dB dB dB
24
MX93002
FIG. 1 MX93002 70 60 50 NDR(dB) 40 30 20 10 0 -80 FIG. 2 MX93002 70 60 50 NDR(dB) 40 30 20 10 0 -80 DA1 & DA2 Linear Format SNDR Characteristic AD1 & AD2 Linear Format SNDR Characteristic
-70
-60
-50
-40 Vin(dB)
-30
-20
-10
0
-70
-60
-50
-40 Vin(dB)
-30
-20
-10
0
25
MX93002
FIG. 3 MX93002 AD1 & AD2 Frequence Response 0 dB ( 1.02KHz as 0dB reference ) -5 -10 -15 -20 -25 -30
0
500
1000
1500 2000 2500 Frequence(Hz) DA1 & DA2 Frequence
3000
3500
4000
FIG. 4 MX93002 2 dB ( 1.02KHz as 0dB reference ) 0 -2 -4 -6 -8 -10 -12 Response
0
500
1000
1500 2000 2500 Frequence(Hz)
3000
3500
4000
26
MX93002
FIG. 5 3500 3000 2500 2000 1500 1000 PATH : MIC => PRE-PGA(0dB) => ALC => AD1-PGA(0dB) => AD1 500 0 0 FIG. 6 MX93002 11/6/97 40 35 30 PATH : MIC => PRE-PGA(0dB) => ALC => AD1-PGA(0dB) => AD1 GAIN (dB) 25 20 15 10 5 0 0 42.4dB 40dB 38.4dB 34.1dB 31dB 500 1000 1500 2000 VIN(mVpp)/1.02KHz 2500 3000 ALC (R/C=560K/10uF) Characteristic MX93002 ALC (R/C=560K/10uF) 42.4dB 40dB 38.4dB 34.1dB 31dB Characteristic
VOUT(mVpp)
500
1000 1500 2000 VIN(mVpp)/1.02KHz
2500
3000
27
MX93002
FIG. 7 MX93002 60 50 SNDR(dB) 40 30 20 10 PATH : MIC => PRE-PGA(0dB) => ALC => AD1-PGA(0dB) => AD1 0 FIG. 8 44 42 40 Gain (dB) 38 36 34 32 30 34.1dB 40dB 42.4dB 38.4dB MX93002 ALC (C=10uF) Characteristic Gain VS Resistor 0 500 1000 1500 2000 VIN(mVpp)/1.02KHz 2500 3000 38.4dB 40dB 42.4dB ALC (R/C=560K/10uF) Characteristic
31dB 34.1dB
31dB 0 200 400 600 800 Resistor (K Ohms) 1000 1200
28
MX93002
FIG. 9 10 3 MX93002 ALC Attack Time Characteristic
ttack Time(ms)
10
2
Path : DA1 => LPFC1 => MIC => ALC(40dB Gain) => AD1 +18dB(3 => 23.8mVpp) +42dB(3 => 378mVpp) +24dB(3 => 47.5mVpp) +30dB(3 => 94.9mVpp) +36dB(3 => 189mVpp)
V1 V2
Test Signal = 20*log ( V2 / V1)
10
1
10 FIG. 10
0
10
1
Capacitor(uF)
10
2
10
3
MX93002 10
3
ALC Release
Time
Characteristic -42dB(378 => 3mVpp) -36dB(189 => 3mVpp) -30dB(94.9 => 3mVpp) -24dB(47.5 => 3mVpp) -18dB(23.8 => 3mVpp)
V1 V2
elease Time(ms)
10
2
Test Signal = 20*log ( V2 / V1)
10
1
Path : DA1 => LPFC1 => MIC => ALC(40dB Gain) => AD1 10
2
Resistor(K ohms)
10
3
29
MX93002
FIG. 11 10 1 MX93002 SPK-DRV Total Harmonic Distortion
THD(%)
10 0
PATH : AUX2 => SWH => SWG => SPKP/N Vout (SPKP/N) = 2*Vin (AUX2) ( AVDD = VDD = 5VDC, RL = 8.2 )
10 -1
10 -2 -1 10 FIG. 12 10
1
10 Vin(Vpp) MX93002 LIN-DRV Total Harmonic Distortion
0
10
1
10 THD(%)
0
PATH : AUX2 => SWK => LOUTP/N Vout (LOUTP/N) = 2*Vin (AUX2) (AVDD = VDD = 5VDC , RL = 600 )
10
-1
10
-2
10
-3
10
-1
10 Vin(Vpp)
0
10
1
30
MX93002
NOTE 1 : PRE-PGA gain step; from -15dB to 22dB 1111 21dB 0111 3.0dB 1110 18dB 0110 1.5dB 1101 15dB 0101 0dB 1100 12dB 0100 -3dB 1011 9dB 0011 -6dB 1010 7.5dB 0010 -9dB 1001 6dB 0001 -12dB 1000 4.5dB 0000 -15dB
NOTE 2 : AD1-PGA gain step; from 0dB to 18dB 00 0dB 01 4dB 10 8dB 11 18dB
NOTE 3 : AD2-PGA gain step; from -6dB to 39dB; 3dB/step 1111 39dB 0111 15dB 1110 36dB 0110 12dB 1101 33dB 0101 9dB 1100 30dB 0100 6dB 1011 27dB 0011 3dB 1010 24dB 0010 0dB 1001 21dB 0001 -3dB 1000 18dB 0000 -6dB
NOTE 4 : LIN-DRV gain step; from 0dB to 22.5dB; 1.5dB/step 1111 22.5dB 0111 10.5dB 1110 21dB 0110 9dB 1101 19.5dB 0101 7.5dB 1100 18dB 0100 6dB 1011 16.5dB 0011 4.5dB 1010 15dB 0010 3dB 1001 13.5dB 0001 1.5dB 1000 12dB 0000 0dB
NOTE 5 : SPK-DRV gain step; from 0dB to 6dB; 2dB/step 00 0dB 01 2dB 10 4dB 11 6dB
NOTE 6 : ATT1 (Attenuator 1) gain step; from 0dB to -45dB 1111 -45 dB 0111 -12 dB 1110 -39 dB 0110 -9 dB 1101 -33 dB 0101 -7.5 dB 1100 -27 dB 0100 -6 dB 1011 -24 dB 0011 -4.5 dB 1010 -21 dB 0010 -3 dB 1001 -18 dB 0001 -1.5 dB 1000 -15 dB 0000 0 dB
NOTE 7 : 1. SWE, SWJ and SWL can not be turned on at the same time; 2. SWJ and SWN can not be turned on at the same time; 3. If SWE, SWJ or SWL is turned on, then SWK will be taken as an output port; 4. If SWK is taken as an input port, SWK, SWE, SWJ and SWL cannot be turned on at the same time;
31
MX93002
Physical Dimensions
44-PIN PQFP
Item A B C D E F G H I J K L M N O P NOTE : Millimeters 13.20 0.20 10.00 0.05 10.00 0.05 13.20 0.20 8.00 [ REF ] 1.00 [ REF ] 1.00 [ REF ] .30 [ TYP. ] .80 [ TYP. ] 1.6 .1 [ TYP. ] 0.80 .1 [ TYP. ] 0.15 [ TYP. ] 0.120 MAX. 2.55 MAX. 0.25 0.1 2.55 MAX. Inches 0.5196 0.008 0.3937 0.002 0.3937 0.002 0.5196 0.008 0.3149 0.0393 [ REF ] 0.0393 [ REF ] 0.0118 [ TYP. ] 0.0314 [ TYP. ] 0.06629 0.004 0.0314 0.004 0.006 [ TYP. ] 0.0040 MAX. 0.100 MAX. 0.0100 0.004 0.100 MAX.
33 34 23 22
A B
E
C
D
44
12 1 11
F
G
H
I J
Each lead centerline is located within .25mm [ .01 inch ] of its true position [ TP ] at a maximum material condition .
N L M K
P O
44-PIN PLCC
Item A B C D E F G H I J K L M N NOTE : Millimeters 17.53 0.12 16.59 0.12 16.59 0.12 17.53 0.12 1.95 4.70 MAX. 2.25 0.25 0.51 MIN. 1.27 [ TYP. ] 0.71 0.1 0.46 0.10 15.50 0.51 0.63 R 0.25 [ TYP. ] Inches 0.690 0.005 0.653 0.005 0.653 0.005 0.690 0.005 0.077 0.185 MAX. 0.100 0.010 0.020 MIN. 0.050 [ TYP. ] 0.028 0.004 0.018 0.004 0.610 0.020 0.025 R 0.010 [ TYP. ]
7 6
A B
1 44 40
39
13
33
C
D
17
29
18
28
Each lead centerline is located within .25mm [ .01 inch ] of its true position [ TP ] at a maximum material condition . F G
E N H I K L J M
32
MX93002
Ordering Information
MX 93 002 F C
MXIC Company Prefix
Product Number
Commercial 0 ~ 70 J
Family Prefix
Package Type F : PQFP Q : PLCC
MACRONIX INTERNATIONAL CO., LTD.
No. 3 Creation Road III, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. TEL : (03)578-8888 FAX : (03)578-8887
Taipei Office :
12F, No. 4, Sec.32 3, Min-Chuan E. Rd., Taipei, Taiwan, R.O.C. TEL : (02)2509-3300 FAX : (02)2509-2200
MACRONIX INC.
1348 Ridder Park Drive, San Jose, CA95131 U.S.A. TEL : (408)453-8088 FAX : (408)453-8488
MACRONIX JAPAN
NKF Bld. 8F, 1-2 Higashida-cho, Kawasaki-ku, Kawasaki-shi, Kanagawa 210, Japan TEL : (044)246-9100 FAX : (044)246-9105
33
MX93002
ECN (Engineering Change Notice)
February 17, 1998 Ver 2.1 1. Change the diagram of the MX93002 about SPK-DRV (page 3) Ver 2.0 : ATT1/ATT2 SPK-DRV ( with 0, 3, 6, 9dB gain ) Ver 2.1 : D/A-PGA ( with 0, 2, 4, 6dB gain ) ATT1/ATT2 SPK-DRV 2. Change NOTE 5 and " page-9 line 13" DA-PGA gain from 0, 3, 6, 9dB to 0, 2, 4, 6dB 3. Change the figure of AD1/AD2 and DA1/DA2 frequency response (FIG. 3/FIG. 4) 4. Change the font size of FIG.1 to FIG. 12 5. Change page-22 line 10 form " FIG. 2" to " FIG. 3" and page-22 line 35 form " FIG. 3" to " FIG. 4" 6. Change the specification of DA path characteristic (page 23) Ver 2.0 PARAMETER 60Hz ~ 300Hz 300Hz ~ 3400Hz 3400Hz ~ 3600Hz 3600Hz ~ 3800Hz Ver 2.1 PARAMETER 60Hz ~ 300Hz 300Hz ~ 2800Hz 3000Hz 3200Hz 3400Hz 3600Hz 3800Hz MIN - 0.6 -1.1 -2.1 -3.7 -6.3 -10 TYP -0.1 + 0.1 MAX UNITS dB dB dB dB dB dB dB MIN TYP 0.2 0.8 -0.26 -12.4 0.8 MAX UNITS dB dB dB dB
March 17, 1998 Ver 2.2 ------ Modify the description of " The Timing Diagram of CODEC Function" 1. Change page-21 about more detailed description of register R/W. 2. Change page-20 " Master Clock, Frame Sync. & Data Timing Diagram" June 8, 1998 Ver 2.3 ------ Modify the bypass and timing description of " CP" pin and FUNCTION DESCRIPTION 1. Change page-6 BASIC COMPONENTS REQUIRED about the value of CP 2. Change page-21 " The Timing Description of CODEC Function" of VAG; from " 1.8ms" to " 0.5ms, 1.8ms and 2.2ms" and add " @ the lock-in time of PLL : MAX 5.5ms; MIN 1.5ms" to the end of page 3. Add " PIN DESCRIPTION" about CP in page-4, see the end of page-21 about the lock-in time of PLL 4. In Page 7, the power-down mode description is modified as follows, " . The MX93002 will recover from power-down mode when MCLK keeps a consistent clock (1.536 or 2.048MHz)" June 25, 1998 Ver 2.4 1. Change the value of CP in Page-6. 2. Correct typing error from C14 to C17 in Page-3 (Block Diagram) and Page-6 (Basic Component Required). 3. Correct typing error from " 2 address" to " 3 addresses" in Page-10. 4. Correct readings of item-L, O, P of 44-QFP package dimension description in Page-31. 5. More detail descriptions about The Timing Diagram/Description of CODEC Function in Page-21 and Page-22.
34
MX93002
6. More detail description for Fig-9 and Fig-10 in Page-29. September 16, 1998 Ver 2.5 1. Revise Power Consumption Specification in Page-11; 2. Revise Power Supply Specification in Page-15; 3. Revise Analog Output Ports Specification in Page-16; 4. Revise Gain Variation and Attenuator Specifications in Page-17; 5. Change the description: " ... switches SWF and SWH are opened, then attenuator will be muted to -70dB If automatically; ... to " ... switches SWF and SWH are opened, then attenuator will be muted to -57dB " If automatically; ... in Page-9; " 6. Change the description: " ... SPK-MUTE ) D(4) = 1 : force SPK-DRV mute to -70dB, D(4) = 0 : force SPK-DRV ( un-mute ... to " ... SPK-MUTE ) D(4) = 1 : force SPK-DRV mute to -57dB, D(4) = 0 : force SPK-DRV un-mute ... in " ( " Page-14; 7. Revise A/D Path Characteristics in Page-23; 8. Revise D/A Path Characteristics in Page-23; 9. Revise Noise Characteristics in Page-24;
35

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